Synchronous dynamic random access memory (SDRAM) devices operate by accessing memory cells in synchronization with a clock signal. The access speed of the device is therefore dependant upon the frequency of the clock. An increase in the clock frequency, therefore, will increase access speed. A problem is experienced when the clock frequency exceeds the process speed of internal memory cell access operations. For example, to access a column of a memory array, an address signal is decoded and column select circuitry is activated. A problem is experienced when the clock frequency exceeds the time needed to complete an access operation of a previous memory column. Thus, if an access is not completed prior to decoding a new column address, the currently accessed column may be prematurely closed.
To avoid some of the timing problems experienced in SDRAMs, the column address decode operation can be pipelined. Additionally, a column select latch can be used to latch a currently accessed memory column while the address of a new column is concurrently decoded, see 250 Mbyte/sec Synchronous DRAM Using a 3-Stage-Pipelined Architecture, [Nagase] Takai et al., 1993 Symposium on VLSI Circuits-Digest of Tecnical Papers, pages 59-60 (May 19-21, 1993) incorporated herein by reference. The problem with this type of column decode and select circuitry is that a column is selected when a new select signal is latched. Thus, a new address must either be delayed from being latched until a current column access operation is completed, or slower clock frequencies must be used. Further, [Nagase] Takai et al. describes an SDRAM which uses a latch connected between a column decode circuit and the memory array. Thus, 256 latch circuits are required in a memory having eight address lines.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a SDRAM having a pipelined address decode which can efficiently delay a new column address until a current access operation is completed. Such a memory device will allow the use of higher clock frequencies.